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authorEli Friedman <efriedma@quicinc.com>2021-07-08 16:14:33 -0700
committerEli Friedman <efriedma@quicinc.com>2021-07-21 10:58:40 -0700
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parentf984ac2715f71c38a7872fa2c2ad535b3d4fa285 (diff)
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[SelectionDAG] Fix the representation of ISD::STEP_VECTOR.
The existing rule about the operand type is strange. Instead, just say the operand is a TargetConstant with the right width. (Legalization ignores TargetConstants, so it doesn't matter if that width is legal.) Highlights: 1. I had to substantially rewrite the AArch64 isel patterns to expect a TargetConstant. Nothing too exotic, but maybe a little hairy. Maybe worth considering a target-specific node with some dagcombines instead of this complicated nest of isel patterns. 2. Our behavior on RV32 for vectors of i64 has changed slightly. In particular, we correctly preserve the width of the arithmetic through legalization. This changes the DAG a bit. Maybe room for improvement here. 3. I explicitly defined the behavior around overflow. This is necessary to make the DAGCombine transforms legal, and I don't think it causes any practical issues. Differential Revision: https://reviews.llvm.org/D105673
Diffstat (limited to 'llvm/lib/Support/OptimizedStructLayout.cpp')
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