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| author | Sanjay Patel <spatel@rotateright.com> | 2021-05-03 08:17:14 -0400 |
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| committer | Sanjay Patel <spatel@rotateright.com> | 2021-05-03 08:39:20 -0400 |
| commit | 1b24f35f843cd58ea22ec3968d0d2589c5bdc2c9 (patch) | |
| tree | e16a48dead2cb63273627bb2f6eb71a51c07fb4c /llvm/lib/Support/MemoryBuffer.cpp | |
| parent | ab7316f1c64c3530a6eca2e449c2dd734e83498e (diff) | |
| download | llvm-1b24f35f843cd58ea22ec3968d0d2589c5bdc2c9.zip llvm-1b24f35f843cd58ea22ec3968d0d2589c5bdc2c9.tar.gz llvm-1b24f35f843cd58ea22ec3968d0d2589c5bdc2c9.tar.bz2 | |
[InstCombine] improve demanded bits analysis of left-shifted operand
If we don't demand high bits, then we also don't care about those
high bits of a left-shift operand regardless of shift amount.
I noticed the sext/trunc pattern in a motivating example.
It seems like there should be a low-bits with right-shift sibling,
but I haven't looked at that yet.
https://alive2.llvm.org/ce/z/JuS6jc
https://rise4fun.com/Alive/Trm (not sure how to use 'width' with Alive1)
https://alive2.llvm.org/ce/z/gRadbF
Differential Revision: https://reviews.llvm.org/D101489
Diffstat (limited to 'llvm/lib/Support/MemoryBuffer.cpp')
0 files changed, 0 insertions, 0 deletions