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| author | Renato Golin <renato.golin@linaro.org> | 2014-09-26 16:14:29 +0000 |
|---|---|---|
| committer | Renato Golin <renato.golin@linaro.org> | 2014-09-26 16:14:29 +0000 |
| commit | 36c626e33f85a8146e6840c65a03f0798a33b2a8 (patch) | |
| tree | 1754fc3a185c19e8ded0afde22fbdcb3ac7b42d2 /llvm/lib/Support/MathExtras.cpp | |
| parent | 11eab6120d9e50512da6b39dc9c6c60b4ca722ce (diff) | |
| download | llvm-36c626e33f85a8146e6840c65a03f0798a33b2a8.zip llvm-36c626e33f85a8146e6840c65a03f0798a33b2a8.tar.gz llvm-36c626e33f85a8146e6840c65a03f0798a33b2a8.tar.bz2 | |
Elide repeated register operand in Thumb1 instructions
This patch makes the ARM backend transform 3 operand instructions such as
'adds/subs' to the 2 operand version of the same instruction if the first
two register operands are the same.
Example: 'adds r0, r0, #1' will is transformed to 'adds r0, #1'.
Currently for some instructions such as 'adds' if you try to assemble
'adds r0, r0, #8' for thumb v6m the assembler would throw an error message
because the immediate cannot be encoded using 3 bits.
The backend should be smart enough to transform the instruction to
'adds r0, #8', which allows for larger immediate constants.
Patch by Ranjeet Singh.
llvm-svn: 218521
Diffstat (limited to 'llvm/lib/Support/MathExtras.cpp')
0 files changed, 0 insertions, 0 deletions