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| author | Heejin Ahn <aheejin@gmail.com> | 2018-04-27 22:23:11 +0000 |
|---|---|---|
| committer | Heejin Ahn <aheejin@gmail.com> | 2018-04-27 22:23:11 +0000 |
| commit | d20d0648ed65eb13a133ae871a649a28add04717 (patch) | |
| tree | 94e9c1de92045c41eff9aac17b388f8fe1658b02 /llvm/lib/Support/LockFileManager.cpp | |
| parent | d656410293d4aacd2dad3e0038032b03d84eb140 (diff) | |
| download | llvm-d20d0648ed65eb13a133ae871a649a28add04717.zip llvm-d20d0648ed65eb13a133ae871a649a28add04717.tar.gz llvm-d20d0648ed65eb13a133ae871a649a28add04717.tar.bz2 | |
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor
Summary:
D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006).
Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.
(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)
Reviewers: RKSimon, jgravelle-google
Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D46161
llvm-svn: 331092
Diffstat (limited to 'llvm/lib/Support/LockFileManager.cpp')
0 files changed, 0 insertions, 0 deletions