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| author | Craig Topper <craig.topper@intel.com> | 2018-12-28 19:19:39 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-12-28 19:19:39 +0000 |
| commit | f814d28eb30f937c9604fdcca83efe1768c0ecf1 (patch) | |
| tree | c25430de70bebe8189950caedcec6a8a8e9fbd5d /llvm/lib/Support/Error.cpp | |
| parent | 4ce05801c75ea5123434fd2a919c83974c8904e6 (diff) | |
| download | llvm-f814d28eb30f937c9604fdcca83efe1768c0ecf1.zip llvm-f814d28eb30f937c9604fdcca83efe1768c0ecf1.tar.gz llvm-f814d28eb30f937c9604fdcca83efe1768c0ecf1.tar.bz2 | |
[X86] Directly emit X86ISD::PMULUDQ from the ReplaceNodeResults handling of v2i8/v2i16/v2i32 multiply.
Previously we emitted a multiply and some masking that was supposed to matched to PMULUDQ, but the masking could sometimes be removed before we got a chance to match it. So instead just emit the PMULUDQ directly.
Remove the DAG combine that was added when the ReplaceNodeResults code was originally added. Add a new DAG combine to avoid regressions in shrink_vmul.ll
Some of the shrink_vmul.ll test cases now pick PMULUDQ instead of PMADDWD/PMULLD, but I think this should be an improvement on most CPUs.
I think all of this can go away if/when we switch to -x86-experimental-vector-widening-legalization
llvm-svn: 350134
Diffstat (limited to 'llvm/lib/Support/Error.cpp')
0 files changed, 0 insertions, 0 deletions