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| author | Sanjay Patel <spatel@rotateright.com> | 2020-08-11 20:27:50 -0400 |
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| committer | Sanjay Patel <spatel@rotateright.com> | 2020-08-11 20:30:02 -0400 |
| commit | b0b95dab1ce21d93f3d62bc37256da9f38cff616 (patch) | |
| tree | 8b68eceaf7a1935ab9a07247e242494c9f1c4605 /llvm/lib/Support/Compression.cpp | |
| parent | 2985c02f798ba8248a9168a9f33a74d90c0c5445 (diff) | |
| download | llvm-b0b95dab1ce21d93f3d62bc37256da9f38cff616.zip llvm-b0b95dab1ce21d93f3d62bc37256da9f38cff616.tar.gz llvm-b0b95dab1ce21d93f3d62bc37256da9f38cff616.tar.bz2 | |
[VectorCombine] add safety check for 0-width register
Based on post-commit discussion in D81766, Hexagon sets this to "0".
I'll see if I can come up with a test, but making the obvious
code fix first to unblock that target.
Diffstat (limited to 'llvm/lib/Support/Compression.cpp')
0 files changed, 0 insertions, 0 deletions