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author | QingShan Zhang <qshanz@cn.ibm.com> | 2020-08-07 04:53:37 +0000 |
---|---|---|
committer | QingShan Zhang <qshanz@cn.ibm.com> | 2020-08-07 04:58:03 +0000 |
commit | 3359ea62edcc5f1d5831bebc2075746031cd22c5 (patch) | |
tree | 889cfd698b51381cb4686244af60a2a1283aa722 /llvm/lib/Support/Compression.cpp | |
parent | 96b02808afa7eb043b9968b07424cc96bc8d94a6 (diff) | |
download | llvm-3359ea62edcc5f1d5831bebc2075746031cd22c5.zip llvm-3359ea62edcc5f1d5831bebc2075746031cd22c5.tar.gz llvm-3359ea62edcc5f1d5831bebc2075746031cd22c5.tar.bz2 |
[Scheduling] Create the missing dependency edges for store cluster
If it is load cluster, we don't need to create the dependency edges(SUb->reg) from SUb to SUa
as they both depend on the base register "reg"
+-------+
+----> reg |
| +---+---+
| ^
| |
| |
| |
| +---+---+
| | SUa | Load 0(reg)
| +---+---+
| ^
| |
| |
| +---+---+
+----+ SUb | Load 4(reg)
+-------+
But if it is store cluster, we need to create it as follow shows to avoid the instruction store
depend on scheduled in-between SUb and SUa.
+-------+
+----> reg |
| +---+---+
| ^
| | Missing +-------+
| | +-------------------->+ y |
| | | +---+---+
| +---+-+-+ ^
| | SUa | Store x 0(reg) |
| +---+---+ |
| ^ |
| | +------------------------+
| | |
| +---+--++
+----+ SUb | Store y 4(reg)
+-------+
Reviewed By: evandro, arsenm, rampitec, foad, fhahn
Differential Revision: https://reviews.llvm.org/D72031
Diffstat (limited to 'llvm/lib/Support/Compression.cpp')
0 files changed, 0 insertions, 0 deletions