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| author | Maciej Gabka <maciej.gabka@arm.com> | 2022-01-26 09:46:32 +0000 |
|---|---|---|
| committer | Andrzej Warzynski <andrzej.warzynski@arm.com> | 2022-01-26 09:57:44 +0000 |
| commit | c5263cd518689bc17690b90aa6bb0a163ef4a56c (patch) | |
| tree | 0f4d2d2a8091b0af123f59c53924a8715feb5aa1 /llvm/lib/Support/CommandLine.cpp | |
| parent | b61c878fc5e5c73243191962516bdeaaac4c923b (diff) | |
| download | llvm-c5263cd518689bc17690b90aa6bb0a163ef4a56c.zip llvm-c5263cd518689bc17690b90aa6bb0a163ef4a56c.tar.gz llvm-c5263cd518689bc17690b90aa6bb0a163ef4a56c.tar.bz2 | |
Restrict performPostLD1Combine to 64 and 128 bit vectors
When wider vectors are used, for example fixed width SVE,
there is no patterns to select AArch64ISD::LD1LANEpost
nodes, so we should do an early exit.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D117674
Diffstat (limited to 'llvm/lib/Support/CommandLine.cpp')
0 files changed, 0 insertions, 0 deletions