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| author | Craig Topper <craig.topper@intel.com> | 2019-02-04 04:44:20 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-02-04 04:44:20 +0000 |
| commit | b5e945c260975c25c5ee423c081c98b78d959e0a (patch) | |
| tree | a86808458f408f47ae0fff346cc096ebc571ae71 /llvm/lib/Support/CommandLine.cpp | |
| parent | 7a2944efe118e58d164c16c9d8f4d4d626a9f11d (diff) | |
| download | llvm-b5e945c260975c25c5ee423c081c98b78d959e0a.zip llvm-b5e945c260975c25c5ee423c081c98b78d959e0a.tar.gz llvm-b5e945c260975c25c5ee423c081c98b78d959e0a.tar.bz2 | |
Recommit r352660 "[X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7."
We now print ST0 as 'st' when generating the clobber list for MS inline assembly in clang. This matches what the gcc reg name list expects.
Original commit message:
This fixes the test case in PR35982 by preventing MMX instructions that read MM0-7 from being moved below EMMS/FEMMS by the post RA scheduler.
Though as discussed in bugzilla, this is not a complete fix. There is still the possibility of reordering in IR or by the pre-RA scheduler.
Differential Revision: https://reviews.llvm.org/D57298
llvm-svn: 353016
Diffstat (limited to 'llvm/lib/Support/CommandLine.cpp')
0 files changed, 0 insertions, 0 deletions