diff options
| author | Caroline Concatto <caroline.concatto@arm.com> | 2022-10-28 15:51:20 +0100 |
|---|---|---|
| committer | Caroline Concatto <caroline.concatto@arm.com> | 2022-11-03 07:35:21 +0000 |
| commit | a20112a74cb34fa967d10e07185167cbc2906c0d (patch) | |
| tree | 351e2bd6595cba899e2e46760990923b73b1f5bc /llvm/lib/Support/CommandLine.cpp | |
| parent | 0041b92cefbb550dd4e754a1ff44337fc32698a2 (diff) | |
| download | llvm-a20112a74cb34fa967d10e07185167cbc2906c0d.zip llvm-a20112a74cb34fa967d10e07185167cbc2906c0d.tar.gz llvm-a20112a74cb34fa967d10e07185167cbc2906c0d.tar.bz2 | |
[AArch64]SME2 instructions that use ZTO operand
This patch adds the assembly/disassembly for the following instructions:
ZERO (ZT0): Zero ZT0.
LDR (ZT0): Load ZT0 register.
STR (ZT0): Store ZT0 register.
MOVT (scalar to ZT0): Move 8 bytes from general-purpose register to ZT0.
(ZT0 to scalar): Move 8 bytes from ZT0 to general-purpose register.
Consecutive:
LUTI2 (single): Lookup table read with 2-bit indexes.
(two registers): Lookup table read with 2-bit indexes.
(four registers): Lookup table read with 2-bit indexes.
LUTI4 (single): Lookup table read with 4-bit indexes.
(two registers): Lookup table read with 4-bit indexes.
(four registers): Lookup table read with 4-bit indexes.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
This patch also adds a new register class and operand for zt0
and a another index operand uimm3s8
Differential Revision: https://reviews.llvm.org/D136088
Diffstat (limited to 'llvm/lib/Support/CommandLine.cpp')
0 files changed, 0 insertions, 0 deletions