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| author | Carl Ritson <carl.ritson@amd.com> | 2022-12-20 15:47:13 +0900 |
|---|---|---|
| committer | Carl Ritson <carl.ritson@amd.com> | 2022-12-20 16:22:14 +0900 |
| commit | 5bc703f755579c0a0e38d8e77146e8e3dd8a955d (patch) | |
| tree | d1119f08c796a8514a954207dc06265c9aa228e1 /llvm/lib/Support/CommandLine.cpp | |
| parent | d393d0d24239aedfd3c8166e7dc188f360104cac (diff) | |
| download | llvm-5bc703f755579c0a0e38d8e77146e8e3dd8a955d.zip llvm-5bc703f755579c0a0e38d8e77146e8e3dd8a955d.tar.gz llvm-5bc703f755579c0a0e38d8e77146e8e3dd8a955d.tar.bz2 | |
[AMDGPU] Replace getPhysRegClass with getPhysRegBaseClass
Accelerate finding the base class for a physical register by
building a statically mapping table from physical registers
to base classes using TableGen.
Replace uses of SIRegisterInfo::getPhysRegClass with
TargetRegisterInfo::getPhysRegBaseClass in order to use
the computed table.
Reviewed By: arsenm, foad
Differential Revision: https://reviews.llvm.org/D139422
Diffstat (limited to 'llvm/lib/Support/CommandLine.cpp')
0 files changed, 0 insertions, 0 deletions