RISCV enable assembly unwinding (#158161)

**Added emulator unwinding support for RISCV files.**

Emulated Instructions:
ADD (addi sp, sp, imm)
STORE (sd ra, offset(sp))
LOAD (ld ra, offset(sp)).

We had to overwrite SetInstructions() since UnwindAssemblyInstEmulation
calls EvaluateInstruction() directly after calling SetInstruction(), but
it never calls ReadInstruction(). This means that the m_decoded member
variable in the instruction emulator is never properly initialized. By
overriding SetInstruction(), we decode the instruction bytes and set
m_decoded directly. This ensures that subsequent emulation (including
unwinding) operates on the correct instruction.

We also had to change the the OpCode GetOpcodeBytes function since
recent changes made it so GetOpcodeBytes will return None for type
eType16_32Tuples (an alternative and longer way, would've been to type
check during the overwritten SetInstruction() and call a DataExtractor
with .GetU16(&offset) to set the inst_data.

Added a test - TestSimpleRiscvFunction (took inspiration from:
[link](https://github.com/llvm/llvm-project/blob/main/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp))

[----------] 1 test from TestRiscvInstEmulation
[ RUN      ] TestRiscvInstEmulation.TestSimpleRiscvFunction
[       OK ] TestRiscvInstEmulation.TestSimpleRiscvFunction (1 ms)
[----------] 1 test from TestRiscvInstEmulation (1 ms total)

[----------] Global test environment tear-down
[==========] 63 tests from 5 test suites ran. (11 ms total)
[  PASSED  ] 63 tests.

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Co-authored-by: Bar Soloveychik <barsolo@fb.com>

0 files changed, 0 insertions, 0 deletions