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| author | Anton Sidorenko <anton.sidorenko@syntacore.com> | 2024-08-09 16:02:27 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-09 16:02:27 +0300 |
| commit | 02645d66f93809f7f52b742987f350793136221f (patch) | |
| tree | ebf1986901501e5155f908e6e9dde51963d7029c /llvm/lib/Support/APFloat.cpp | |
| parent | 0795ab4eba14b7a93c52c06f328c3d4272f3c51e (diff) | |
| download | llvm-02645d66f93809f7f52b742987f350793136221f.zip llvm-02645d66f93809f7f52b742987f350793136221f.tar.gz llvm-02645d66f93809f7f52b742987f350793136221f.tar.bz2 | |
[RISCV] Add Syntacore SCR5 RV32/64 processors definition (#102285)
Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V
processor core.
Overview: https://syntacore.com/products/scr5
Scheduling model will be added in a subsequent PR.
Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev@syntacore.com>
Diffstat (limited to 'llvm/lib/Support/APFloat.cpp')
0 files changed, 0 insertions, 0 deletions