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| author | Visoiu Mistrih Francis <890283+francisvm@users.noreply.github.com> | 2024-02-26 18:25:21 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-26 18:25:21 -0800 |
| commit | b791a51730f145308f3607d0d33038af78138304 (patch) | |
| tree | c70002bfa07ad92fd45ce77acba75736a56516b3 /llvm/lib/ProfileData/Coverage/CoverageMapping.cpp | |
| parent | c11627c2f4d550613a3cb360c89a0cf52d2eb720 (diff) | |
| download | llvm-b791a51730f145308f3607d0d33038af78138304.zip llvm-b791a51730f145308f3607d0d33038af78138304.tar.gz llvm-b791a51730f145308f3607d0d33038af78138304.tar.bz2 | |
[CodeGenSchedule] Don't allow invalid ReadAdvances to be formed (#82685)
Forming a `ReadAdvance` with an entry in the `ValidWrites` list that is
not used by any instruction results in the entire `ReadAdvance` to be
ignored by the scheduler due to an invalid entry.
The `SchedRW` collection code only picks up `SchedWrites` that are
reachable from `Instructions`, `InstRW`, `ItinRW` and `SchedAlias`,
leaving the unreachable ones with an invalid entry (0) in
`SubtargetEmitter::GenSchedClassTables` when going through the list of
`ReadAdvances`
Diffstat (limited to 'llvm/lib/ProfileData/Coverage/CoverageMapping.cpp')
0 files changed, 0 insertions, 0 deletions