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| author | Craig Topper <craig.topper@sifive.com> | 2024-02-04 16:05:51 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-04 16:05:51 -0800 |
| commit | 6590d0fed5180a403c32c991baed56f9d39e045a (patch) | |
| tree | 17d6c96be4207ed4e12de421f9750484191cb30c /llvm/lib/ProfileData/Coverage/CoverageMapping.cpp | |
| parent | f72da9f4fd389951c4d65055f5471e208f256212 (diff) | |
| download | llvm-6590d0fed5180a403c32c991baed56f9d39e045a.zip llvm-6590d0fed5180a403c32c991baed56f9d39e045a.tar.gz llvm-6590d0fed5180a403c32c991baed56f9d39e045a.tar.bz2 | |
[DAGCombiner][ARM] Teach reduceLoadWidth to handle (and (srl (load), C, ShiftedMask)) (#80342)
If we have a shifted mask, we may be able to reduce the load width
to the width of the non-zero part of the mask and use an offset
to the base address to remove the srl. The offset is given by
C+trailingzeros(ShiftedMask).
Then we add a final shl to restore the trailing zero bits.
I've use the ARM test because that's where the existing (and (srl
(load))) tests were.
The X86 test was modified to keep the H register.
Diffstat (limited to 'llvm/lib/ProfileData/Coverage/CoverageMapping.cpp')
0 files changed, 0 insertions, 0 deletions