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| author | Gadi Haber <gadi.haber@intel.com> | 2017-10-24 20:19:47 +0000 |
|---|---|---|
| committer | Gadi Haber <gadi.haber@intel.com> | 2017-10-24 20:19:47 +0000 |
| commit | 323f2e17151a6f3105bf1917f2ca42e168b2ff33 (patch) | |
| tree | f9f88cb820add121001f35f973fba50dea045da3 /llvm/lib/ProfileData/Coverage/CoverageMapping.cpp | |
| parent | f8f4620dc6c1e015a0008f348c35b9da633c8f50 (diff) | |
| download | llvm-323f2e17151a6f3105bf1917f2ca42e168b2ff33.zip llvm-323f2e17151a6f3105bf1917f2ca42e168b2ff33.tar.gz llvm-323f2e17151a6f3105bf1917f2ca42e168b2ff33.tar.bz2 | |
[X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU.
Adding the scheduling information for the Browadwell (BDW) CPU target.
This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target.
We used the scheduling information retrieved from the Broadwell architects in order to create the file.
The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction.
The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175.
Performance fluctuations may be expected due to code alignment effects.
Reviewers: zvi, RKSimon, craig.topper
Differential Revision: https://reviews.llvm.org/D39054
Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01
llvm-svn: 316492
Diffstat (limited to 'llvm/lib/ProfileData/Coverage/CoverageMapping.cpp')
0 files changed, 0 insertions, 0 deletions