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| author | Brandon Bergren <git@bdragon.rtk0.net> | 2020-11-23 19:07:21 -0800 |
|---|---|---|
| committer | Fangrui Song <i@maskray.me> | 2020-11-23 19:07:21 -0800 |
| commit | bb1341161478dc589893cda9f808e5f5b859b5ae (patch) | |
| tree | b6f89c1d5bd65d268f7c1d8c42229bb77a0874cd /llvm/lib/Object/XCOFFObjectFile.cpp | |
| parent | 9194aa88676fbf6d215efbe461abe9ac18bc0ffc (diff) | |
| download | llvm-bb1341161478dc589893cda9f808e5f5b859b5ae.zip llvm-bb1341161478dc589893cda9f808e5f5b859b5ae.tar.gz llvm-bb1341161478dc589893cda9f808e5f5b859b5ae.tar.bz2 | |
[libunwind] Multiple preprocessor fixes on PowerPC*
* Remove misnamed `PPC64_HAS_VMX` in preference of directly checking `defined(__VSX__)`.
libunwind was using "VMX" to mean "VSX". "VMX" is just another name for Altivec, while "VSX" is the vector-scalar extensions first used in POWER7. Exposing a "PPC64_HAS_VMX" define was misleading and incorrect.
* Add `defined(__ALTIVEC__)` guards around vector register operations to fix non-altivec CPUS such as the e5500.
When compiling for certain Book-E processors such as the e5500, we want to skip vector save/restore, as the Altivec registers are illegal on non-Altivec implementations.
* Add `!defined(__NO_FPRS__)` guards around traditional floating-point save/restore.
When compiling for powerpcspe, we cannot access floating point registers, as there aren't any. (The SPE on e500v2 is a 64-bit extension of the GPRs, and it doesn't have the normal floating-point registers at all.)
This fixes building for powerpcspe, although no actual handling for SPE save/restore is written yet.
Reviewed By: MaskRay, #libunwind, compnerd
Differential Revision: https://reviews.llvm.org/D91906
Diffstat (limited to 'llvm/lib/Object/XCOFFObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions
