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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-22 15:02:34 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-22 15:02:34 +0000 |
| commit | 542720b2bc48d243d2eec93157feebc37af0e202 (patch) | |
| tree | 329e82ce7ea94f5afa8290491bd0debe65636265 /llvm/lib/Object/XCOFFObjectFile.cpp | |
| parent | 1b2da771f561affe36eb5eb0c7a3d2862c5a5c1c (diff) | |
| download | llvm-542720b2bc48d243d2eec93157feebc37af0e202.zip llvm-542720b2bc48d243d2eec93157feebc37af0e202.tar.gz llvm-542720b2bc48d243d2eec93157feebc37af0e202.tar.bz2 | |
TableGen: Support physical register inputs > 255
This was truncating register value that didn't fit in unsigned char.
Switch AMDGPU sendmsg intrinsics to using a tablegen pattern.
llvm-svn: 366695
Diffstat (limited to 'llvm/lib/Object/XCOFFObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions