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| author | Jingu Kang <jingu.kang@arm.com> | 2021-06-10 16:02:57 +0100 |
|---|---|---|
| committer | Jingu Kang <jingu.kang@arm.com> | 2021-06-14 15:48:51 +0100 |
| commit | 08ce52ef5e6b879216f8018b920ef5c0621e797d (patch) | |
| tree | 0802a05a627667e711a51ed7573a93b5eff6e014 /llvm/lib/Object/XCOFFObjectFile.cpp | |
| parent | c60dd3b2626a4d9eefd9f82f9a406b0d28d3fd72 (diff) | |
| download | llvm-08ce52ef5e6b879216f8018b920ef5c0621e797d.zip llvm-08ce52ef5e6b879216f8018b920ef5c0621e797d.tar.gz llvm-08ce52ef5e6b879216f8018b920ef5c0621e797d.tar.bz2 | |
[AArch64] Improve SAD pattern
Given a vecreduce_add node, detect the below pattern and convert it to the node
sequence with UABDL, [S|U]ADB and UADDLP.
i32 vecreduce_add(
v16i32 abs(
v16i32 sub(
v16i32 [sign|zero]_extend(v16i8 a), v16i32 [sign|zero]_extend(v16i8 b))))
=================>
i32 vecreduce_add(
v4i32 UADDLP(
v8i16 add(
v8i16 zext(
v8i8 [S|U]ABD low8:v16i8 a, low8:v16i8 b
v8i16 zext(
v8i8 [S|U]ABD high8:v16i8 a, high8:v16i8 b
Differential Revision: https://reviews.llvm.org/D104042
Diffstat (limited to 'llvm/lib/Object/XCOFFObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions