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author | Shubham Sandeep Rastogi <srastogi22@apple.com> | 2025-01-17 09:27:36 -0800 |
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committer | GitHub <noreply@github.com> | 2025-01-17 09:27:36 -0800 |
commit | ee1c85225235c4353555a17b73ba16a2f177265b (patch) | |
tree | b925a70f7bacfdd19149cbe28c8be9df0d3b3fdc /llvm/lib/Object/WasmObjectFile.cpp | |
parent | 4b692a95d103f3ad30d6be1ce6d5dda0bd90bc1f (diff) | |
download | llvm-ee1c85225235c4353555a17b73ba16a2f177265b.zip llvm-ee1c85225235c4353555a17b73ba16a2f177265b.tar.gz llvm-ee1c85225235c4353555a17b73ba16a2f177265b.tar.bz2 |
[DebugInfo][InstrRef] Treat ORRWrr as a copy instr (#123102)
The insturction selector uses the `MachineFunction::copySalvageSSA`
function to insert `DBG_PHIs` or identify a defining instruction for a
copy-like instruction when finalizing Instruction References.
AArch64 has the ORR instruction which is a logical OR with the variants
ORRWrr which refers to a register to register variant, and ORRWrs which
is a register to a shifted register variant.
An ORRWrs where the shift amount is 0, and the zero register ($wzr) is
used is considered a copy, for example:
`$w0 = ORRWrs $wzr, killed $w3, 0`
However an ORRWrr with a zero register is not considered a copy
`$w0 = ORRWrr $wzr, killed $w3`
This causes an issue in the livedebugvalues pass because in aarch64-isel
the instruction is the ORRWrr variant, but is then changed to the ORRWrs
variant before the livedebugvalues pass.
This causes a mismatch between the two passes which leads to a crash in
the livedebugvalues pass.
This patch fixes the issue.
Diffstat (limited to 'llvm/lib/Object/WasmObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions