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| author | Michael Zuckerman <Michael.zuckerman@intel.com> | 2017-09-26 18:49:11 +0000 |
|---|---|---|
| committer | Michael Zuckerman <Michael.zuckerman@intel.com> | 2017-09-26 18:49:11 +0000 |
| commit | 645f777e40c367e5a73acfc400677250a4661b32 (patch) | |
| tree | 66f254de0aa1a78a79c68202a7bb6197cdbe343b /llvm/lib/Object/WasmObjectFile.cpp | |
| parent | 8bf622174d699e9a09bd7de2dc85b2c8fe38f176 (diff) | |
| download | llvm-645f777e40c367e5a73acfc400677250a4661b32.zip llvm-645f777e40c367e5a73acfc400677250a4661b32.tar.gz llvm-645f777e40c367e5a73acfc400677250a4661b32.tar.bz2 | |
[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF{8|16|32} stride 3)
This patch expands the support of lowerInterleavedStore to {8|16|32}x8i stride 3.
LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=3 VF={8|16|32}) .
This patch is part two of two patches and it covers the store (interlevaed) side.
The patch goal is to optimize the following sequence:
a0 a1 a2 a3 a4 a5 a6 a7
b0 b1 b2 b3 b4 b5 b6 b7
c0 c1 c2 c3 c4 c5 c6 c7
into
a0 b0 c0 a1 b1 c1 a2 b2
c2 a3 b3 c3 a4 b4 c4 a5
b5 c5 a6 b6 c6 a7 b7 c7
Reviewers:
zvi
guyblank
dorit
Ayal
Differential Revision: https://reviews.llvm.org/D37117
Change-Id: I56ced8bcbea809a37654060771911ade20246ccc
llvm-svn: 314234
Diffstat (limited to 'llvm/lib/Object/WasmObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions