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author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2025-09-23 09:44:46 -0700 |
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committer | GitHub <noreply@github.com> | 2025-09-23 09:44:46 -0700 |
commit | e45993d9a7ad2c07989d18888e56c5fc3276902f (patch) | |
tree | 58059fa0fb823539cbbd4153b4e9590b351d6498 /llvm/lib/Object/SFrameParser.cpp | |
parent | a584bd98a1ea80c8fa99206edc0622062924603c (diff) | |
download | llvm-e45993d9a7ad2c07989d18888e56c5fc3276902f.zip llvm-e45993d9a7ad2c07989d18888e56c5fc3276902f.tar.gz llvm-e45993d9a7ad2c07989d18888e56c5fc3276902f.tar.bz2 |
[AMDGPU] Fix sub-dword atomic flat saddr store with no D16. NFCI (#160253)
The pattern does not factor saddr. There is no way to write a test
for it because gfx1200 does not have sram-ecc but also no saddr,
and gfx1250 does not fall into this preserving category while has
sram-ecc. Nevertheless, the day we could fix it that would become a
problem. For now it is OK that change does not fail.
That was untested before and it is untested now, but at least t16
block uses t16 patterns.
Diffstat (limited to 'llvm/lib/Object/SFrameParser.cpp')
0 files changed, 0 insertions, 0 deletions