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| author | Sergei Barannikov <barannikov88@gmail.com> | 2025-09-19 20:15:38 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-19 17:15:38 +0000 |
| commit | bf835169a52b792acc9f8ad26141fb3e556b6f71 (patch) | |
| tree | a55d947f45c3f59eb01b2dc9856b9fa81a8f1a9c /llvm/lib/Object/ObjectFile.cpp | |
| parent | cac54a8ad08938a66d4f0ce6114c53cb0ace4499 (diff) | |
| download | llvm-bf835169a52b792acc9f8ad26141fb3e556b6f71.zip llvm-bf835169a52b792acc9f8ad26141fb3e556b6f71.tar.gz llvm-bf835169a52b792acc9f8ad26141fb3e556b6f71.tar.bz2 | |
[AArch64] Remove post-decoding instruction mutations (#156364)
Add `bits<0>` fields to instructions using the ZTR/MPR/MPR8 register
classes. These register classes contain only one register, and it is
not encoded in the instruction. This way, the generated decoder can
completely decode instructions without having to perform a post-decoding
pass to insert missing operands.
Some immediate operands are also not encoded and have only one possible
value "zero". Use this trick for them, too.
Finally, remove `-ignore-non-decodable-operands` option from
`llvm-tblgen` invocation to ensure that non-decodable operands do not
appear in the future.
Diffstat (limited to 'llvm/lib/Object/ObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions