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| author | JF Bastien <jfb@google.com> | 2013-06-09 00:20:24 +0000 |
|---|---|---|
| committer | JF Bastien <jfb@google.com> | 2013-06-09 00:20:24 +0000 |
| commit | 652fa6a8b228a775ac549cabdb493b363ac2f93f (patch) | |
| tree | 7ef41c57e0f42b57546f3cf624436fff653d70aa /llvm/lib/Object/ObjectFile.cpp | |
| parent | 0fc8670cb09564a48efe1afc0e6335f904a4c887 (diff) | |
| download | llvm-652fa6a8b228a775ac549cabdb493b363ac2f93f.zip llvm-652fa6a8b228a775ac549cabdb493b363ac2f93f.tar.gz llvm-652fa6a8b228a775ac549cabdb493b363ac2f93f.tar.bz2 | |
ARM FastISel fix load register classes
The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register.
These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets.
llvm-svn: 183624
Diffstat (limited to 'llvm/lib/Object/ObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions