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| author | Sergei Barannikov <barannikov88@gmail.com> | 2025-09-19 20:37:52 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-19 17:37:52 +0000 |
| commit | 4cace1ff0f9a144de9f46f4521d140080e4e284d (patch) | |
| tree | af623fad1af8a30cbbcf4003627171416522af10 /llvm/lib/Object/ObjectFile.cpp | |
| parent | 4c7ebf825edabb5e0433b312ddac7914028e4488 (diff) | |
| download | llvm-4cace1ff0f9a144de9f46f4521d140080e4e284d.zip llvm-4cace1ff0f9a144de9f46f4521d140080e4e284d.tar.gz llvm-4cace1ff0f9a144de9f46f4521d140080e4e284d.tar.bz2 | |
[ARM] Verify that disassembled instruction is correct (#157360)
This change adds basic `MCInst` verification (checks the number of
operands) and fixes detected bugs.
* `RFE*` instructions have only one operand, but `DecodeRFEInstruction`
added two.
* `DecodeMVEModImmInstruction` and `DecodeMVEVCMP` added a `vpred`
operand, but this is what `AddThumbPredicate` normally does. This
resulted in an extra `vpred` operand.
* `DecodeMVEVADCInstruction` added an extra immediate operand.
* `getARMInstruction` added a `pred` operand to instructions that don't
have one (via `DecodePredicateOperand`).
* `AddThumb1SBit` appended an extra register operand to instructions
that don't modify CPSR (such as `tBL`).
* Instructions in `NEONDup` namespace have `pred` operand that the
generated code successfully decodes. The operand was added once again by
`getARMInstruction`/`getThumbInstruction` via `AddThumbPredicate`.
Functional changes extracted from #156540.
Diffstat (limited to 'llvm/lib/Object/ObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions