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| author | Craig Topper <craig.topper@intel.com> | 2019-04-05 19:27:49 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-04-05 19:27:49 +0000 |
| commit | 7323c2bf850b61b85252e17e6f1f73037c328378 (patch) | |
| tree | bec1eabcb3f5ccd842c2e22472c5a9b90b7faff5 /llvm/lib/Object/Object.cpp | |
| parent | e0bfeb5f24979416144c16e8b99204f5f163b889 (diff) | |
| download | llvm-7323c2bf850b61b85252e17e6f1f73037c328378.zip llvm-7323c2bf850b61b85252e17e6f1f73037c328378.tar.gz llvm-7323c2bf850b61b85252e17e6f1f73037c328378.tar.bz2 | |
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri
Reviewed By: andreadb
Subscribers: hiraditya, lebedev.ri, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60138
llvm-svn: 357801
Diffstat (limited to 'llvm/lib/Object/Object.cpp')
0 files changed, 0 insertions, 0 deletions