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| author | Jim Grosbach <grosbach@apple.com> | 2011-10-21 18:54:25 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-10-21 18:54:25 +0000 |
| commit | 2f2e3c47373ca2ee60d4d0810da3429443fa4aca (patch) | |
| tree | 7ebf77ca316e8c20adb2e21780e78fc603d45e1e /llvm/lib/Object/Object.cpp | |
| parent | 03a173eb71caa9c8835288f8e89a8e765fec19cf (diff) | |
| download | llvm-2f2e3c47373ca2ee60d4d0810da3429443fa4aca.zip llvm-2f2e3c47373ca2ee60d4d0810da3429443fa4aca.tar.gz llvm-2f2e3c47373ca2ee60d4d0810da3429443fa4aca.tar.bz2 | |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
Diffstat (limited to 'llvm/lib/Object/Object.cpp')
0 files changed, 0 insertions, 0 deletions