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| author | Saiyedul Islam <Saiyedul.Islam@amd.com> | 2020-07-01 07:28:47 +0000 |
|---|---|---|
| committer | Saiyedul Islam <Saiyedul.Islam@amd.com> | 2020-07-01 07:40:47 +0000 |
| commit | 91823163955859abbdcad5901d765aeae860939e (patch) | |
| tree | 2a0218130ec3fbb1350c03e325995d90019d318d /llvm/lib/Object/ModuleSymbolTable.cpp | |
| parent | 3ee580d0176f69a9f724469660f1d1805e0b6a06 (diff) | |
| download | llvm-91823163955859abbdcad5901d765aeae860939e.zip llvm-91823163955859abbdcad5901d765aeae860939e.tar.gz llvm-91823163955859abbdcad5901d765aeae860939e.tar.bz2 | |
[AMDGPU] Spill more than wavesize CSR SGPRs
In case of more than wavesize CSR SGPR spills, lanes of reserved VGPR were getting
overwritten due to wrap around.
Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and when one
of the two conditions is true:
1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet reserved.
2. All spill lanes of reserved VGPR(s) are full and another spill lane is required.
Reviewed By: arsenm, kerbowa
Differential Revision: https://reviews.llvm.org/D82463
Diffstat (limited to 'llvm/lib/Object/ModuleSymbolTable.cpp')
0 files changed, 0 insertions, 0 deletions