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authorKai Wang <kai.wang@sifive.com>2020-02-04 22:20:10 +0800
committerKai Wang <kai.wang@sifive.com>2020-03-31 16:16:19 +0800
commit581ba35291a658cd01e2cb39f6d415cac89a7656 (patch)
tree047e1bd37131e7519e7eef3de5be549722fb4052 /llvm/lib/Object/ELF.cpp
parent86b40760278e73710564135be8cd9c2c9e7ff080 (diff)
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[RISCV] ELF attribute section for RISC-V.
Leverage ARM ELF build attribute section to create ELF attribute section for RISC-V. Extract the common part of parsing logic for this section into ELFAttributeParser.[cpp|h] and ELFAttributes.[cpp|h]. Differential Revision: https://reviews.llvm.org/D74023
Diffstat (limited to 'llvm/lib/Object/ELF.cpp')
-rw-r--r--llvm/lib/Object/ELF.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Object/ELF.cpp b/llvm/lib/Object/ELF.cpp
index d1bf469..e58d623 100644
--- a/llvm/lib/Object/ELF.cpp
+++ b/llvm/lib/Object/ELF.cpp
@@ -223,6 +223,9 @@ StringRef llvm::object::getELFSectionTypeName(uint32_t Machine, unsigned Type) {
STRINGIFY_ENUM_CASE(ELF, SHT_MIPS_ABIFLAGS);
}
break;
+ case ELF::EM_RISCV:
+ switch (Type) { STRINGIFY_ENUM_CASE(ELF, SHT_RISCV_ATTRIBUTES); }
+ break;
default:
break;
}