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| author | Craig Topper <craig.topper@sifive.com> | 2022-06-16 14:45:44 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-06-16 14:55:14 -0700 |
| commit | e6c7a3a54ffaf0001017f619faf2fa260fb517b4 (patch) | |
| tree | f1cba8db186c9191593f41312c73127c31780b75 /llvm/lib/Object/COFFObjectFile.cpp | |
| parent | 011e0604ebc9d85db3585ebb2f63df465f726417 (diff) | |
| download | llvm-e6c7a3a54ffaf0001017f619faf2fa260fb517b4.zip llvm-e6c7a3a54ffaf0001017f619faf2fa260fb517b4.tar.gz llvm-e6c7a3a54ffaf0001017f619faf2fa260fb517b4.tar.bz2 | |
[SelectionDAG] Don't apply MinRCSize constraint in InstrEmitter::AddRegisterOperand for IMPLICIT_DEF sources.
MinRCSize is 4 and prevents constrainRegClass from changing the
register class if the new class has size less than 4.
IMPLICIT_DEF gets a unique vreg for each use and will be removed
by the ProcessImplicitDef pass before register allocation. I don't
think there is any reason to prevent constraining the virtual register
to whatever register class the use needs.
The attached test case was previously creating a copy of IMPLICIT_DEF
because vrm8nov0 has 3 registers in it.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D128005
Diffstat (limited to 'llvm/lib/Object/COFFObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions