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| author | Craig Topper <craig.topper@intel.com> | 2020-06-11 12:18:52 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-06-11 12:20:29 -0700 |
| commit | 269d843720382a8beafdf156cd01f9791faff66c (patch) | |
| tree | bf2b99ae75040e6bf9455a26e86fe869b8458ac4 /llvm/lib/Object/COFFObjectFile.cpp | |
| parent | 12459ec92686573e68ba9b18dd5ea90a1a4e9bc7 (diff) | |
| download | llvm-269d843720382a8beafdf156cd01f9791faff66c.zip llvm-269d843720382a8beafdf156cd01f9791faff66c.tar.gz llvm-269d843720382a8beafdf156cd01f9791faff66c.tar.bz2 | |
[X86] Replace TB with PS on instructions that are documented in the SDM with 'NP'
'NP' means that the instruction is not recognized with a 66, F2 or F3
prefix. It will either #UD or decode to a different instruction.
All of the cases are here should fall into the #UD variety since
we should be detecting the collision with other instructions when
we build the disassembler tables.
Diffstat (limited to 'llvm/lib/Object/COFFObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions