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| author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2019-07-09 16:48:42 +0000 |
|---|---|---|
| committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2019-07-09 16:48:42 +0000 |
| commit | b2d24bd5400dcabced806a11066854bf62349f4f (patch) | |
| tree | c8c8bb0b61b37cf5933a6697a0276574375a5873 /llvm/lib/Object/Binary.cpp | |
| parent | 114d2db49b133594257ba0d74cc433f23759bac8 (diff) | |
| download | llvm-b2d24bd5400dcabced806a11066854bf62349f4f.zip llvm-b2d24bd5400dcabced806a11066854bf62349f4f.tar.gz llvm-b2d24bd5400dcabced806a11066854bf62349f4f.tar.bz2 | |
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding
the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class
exclusive of the CSRs, and used this regclass while lowering the return instruction.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D63924
llvm-svn: 365512
Diffstat (limited to 'llvm/lib/Object/Binary.cpp')
0 files changed, 0 insertions, 0 deletions