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| author | John Brawn <john.brawn@arm.com> | 2015-08-13 10:48:22 +0000 |
|---|---|---|
| committer | John Brawn <john.brawn@arm.com> | 2015-08-13 10:48:22 +0000 |
| commit | 68acdcb435ba0e4413f74d3eab16af22d4a49695 (patch) | |
| tree | 839280a3a222f73d7ac03aef47d4bc3b28458254 /llvm/lib/MC/MCDisassembler/Disassembler.cpp | |
| parent | a58332fb5b656c7346564f6741fc6ddd6afd59bc (diff) | |
| download | llvm-68acdcb435ba0e4413f74d3eab16af22d4a49695.zip llvm-68acdcb435ba0e4413f74d3eab16af22d4a49695.tar.gz llvm-68acdcb435ba0e4413f74d3eab16af22d4a49695.tar.bz2 | |
[ARM] Reorganise and simplify thumb-1 load/store selection
Other than PC-relative loads/store the patterns that match the various
load/store addressing modes have the same complexity, so the order that they
are matched is the order that they appear in the .td file.
Rearrange the instruction definitions in ARMInstrThumb.td, and make use of
AddedComplexity for PC-relative loads, so that the instruction matching order
is the order that results in the simplest selection logic. This also makes
register-offset load/store be selected when it should, as previously it was
only selected for too-large immediate offsets.
Differential Revision: http://reviews.llvm.org/D11800
llvm-svn: 244882
Diffstat (limited to 'llvm/lib/MC/MCDisassembler/Disassembler.cpp')
0 files changed, 0 insertions, 0 deletions