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author | Yonghong Song <yhs@fb.com> | 2020-04-19 15:19:06 -0700 |
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committer | Yonghong Song <yhs@fb.com> | 2020-04-20 19:54:51 -0700 |
commit | 3cb7e7bf959dcd3b8080986c62e10a75c7af43f0 (patch) | |
tree | ff0bcebf4b3b28a7c24947bac929dfb6fa257eb1 /llvm/lib/MC/MCCodeView.cpp | |
parent | c2d86e1f3044abb295796c8267c7b9057f54a067 (diff) | |
download | llvm-3cb7e7bf959dcd3b8080986c62e10a75c7af43f0.zip llvm-3cb7e7bf959dcd3b8080986c62e10a75c7af43f0.tar.gz llvm-3cb7e7bf959dcd3b8080986c62e10a75c7af43f0.tar.bz2 |
BPF: fix a CORE optimization bug
For the test case in this patch like below
struct t { int a; } __attribute__((preserve_access_index));
int foo(void *);
int test(struct t *arg) {
long param[1];
param[0] = (long)&arg->a;
return foo(param);
}
The IR right before BPF SimplifyPatchable phase:
%1:gpr = LD_imm64 @"llvm.t:0:0$0:0"
%2:gpr = LDD killed %1:gpr, 0
%3:gpr = ADD_rr %0:gpr(tied-def 0), killed %2:gpr
STD killed %3:gpr, %stack.0.param, 0
After SimplifyPatchable phase, the incorrect IR is generated:
%1:gpr = LD_imm64 @"llvm.t:0:0$0:0"
%3:gpr = ADD_rr %0:gpr(tied-def 0), killed %1:gpr
CORE_MEM killed %3:gpr, 306, %0:gpr, @"llvm.t:0:0$0:0"
Note that CORE_MEM pseudo op is introduced to encode
memory operations related to CORE. In the above, we intend
to check whether we have a store like
*(%3:gpr + 0) = ...
and if this is the case, we could replace it with
*(%0:gpr + @"llvm.t:0:0$0:0"_ = ...
Unfortunately, in the above, IR for the store is
*(%stack.0.param + 0) = %3:gpr
and transformation should not happen.
Note that we won't have problem if the actual CORE
dereference (arg->a) happens.
This patch fixed the problem by skip CORE optimization if
the use of ADD_rr result is not the base address of the store
operation.
Differential Revision: https://reviews.llvm.org/D78466
Diffstat (limited to 'llvm/lib/MC/MCCodeView.cpp')
0 files changed, 0 insertions, 0 deletions