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| author | Alexander Timofeev <alexander.timofeev@amd.com> | 2022-06-21 10:57:58 +0200 |
|---|---|---|
| committer | Alexander Timofeev <alexander.timofeev@amd.com> | 2022-07-14 23:59:02 +0200 |
| commit | 2e29b0138ca243c7d288622524a004c84acbbb9e (patch) | |
| tree | 94c9bdfffd3ba7057fd5df6fdde48514a16e2c22 /llvm/lib/MC/ELFObjectWriter.cpp | |
| parent | 5b0788fef86ed7008a11f6ee19b9d86d42b6fcfa (diff) | |
| download | llvm-2e29b0138ca243c7d288622524a004c84acbbb9e.zip llvm-2e29b0138ca243c7d288622524a004c84acbbb9e.tar.gz llvm-2e29b0138ca243c7d288622524a004c84acbbb9e.tar.bz2 | |
[AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable.
Since the divergence-driven instruction selection has been enabled for AMDGPU,
all the uniform instructions are expected to be selected to SALU form, except those not having one.
VGPR to SGPR copies appear in MIR to connect values producers and consumers. This change implements an algorithm
that evolves a reasonable tradeoff between the profit achieved from keeping the uniform instructions in SALU form
and overhead introduced by the data transfer between the VGPRs and SGPRs.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D128252
Diffstat (limited to 'llvm/lib/MC/ELFObjectWriter.cpp')
0 files changed, 0 insertions, 0 deletions