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| author | Alex Bradbury <asb@lowrisc.org> | 2019-01-31 22:48:38 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2019-01-31 22:48:38 +0000 |
| commit | d834d8301d7d2219f4c6c29e7e0906d18a52fbe3 (patch) | |
| tree | c42e61ebbeef8b5566ecb6a37aee8dbc903d5171 /llvm/lib/IR/Module.cpp | |
| parent | c0affde863665ac198366956a56742321537f319 (diff) | |
| download | llvm-d834d8301d7d2219f4c6c29e7e0906d18a52fbe3.zip llvm-d834d8301d7d2219f4c6c29e7e0906d18a52fbe3.tar.gz llvm-d834d8301d7d2219f4c6c29e7e0906d18a52fbe3.tar.bz2 | |
[RISCV] Add RV64F codegen support
This requires a little extra work due tothe fact i32 is not a legal type. When
call lowering happens post-legalisation (e.g. when an intrinsic was inserted
during legalisation). A bitcast from f32 to i32 can't be introduced. This is
similar to the challenges with RV32D. To handle this, we introduce
target-specific DAG nodes that perform bitcast+anyext for f32->i64 and
trunc+bitcast for i64->f32.
Differential Revision: https://reviews.llvm.org/D53235
llvm-svn: 352807
Diffstat (limited to 'llvm/lib/IR/Module.cpp')
0 files changed, 0 insertions, 0 deletions