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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-18 14:08:01 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-18 14:08:01 +0000 |
| commit | c4b8d367a8bc9bf39fb0c8ebf08ce7e3f53aa9d3 (patch) | |
| tree | ce34a0f3cbd5ac525a2a92fde6e66ee902cc8e4b /llvm/lib/IR/Module.cpp | |
| parent | a840a465579a91418575c77ca6c04ded28f55b1a (diff) | |
| download | llvm-c4b8d367a8bc9bf39fb0c8ebf08ce7e3f53aa9d3.zip llvm-c4b8d367a8bc9bf39fb0c8ebf08ce7e3f53aa9d3.tar.gz llvm-c4b8d367a8bc9bf39fb0c8ebf08ce7e3f53aa9d3.tar.bz2 | |
[X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore scheduler classes
Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc.
Fixes BtVer2/SLM which have different behaviours for GPR stores.
llvm-svn: 332718
Diffstat (limited to 'llvm/lib/IR/Module.cpp')
0 files changed, 0 insertions, 0 deletions