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| author | Brox Chen <broxigarchen@outlook.com> | 2024-08-13 12:23:39 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-13 12:23:39 -0400 |
| commit | afd42fb3038904e8c09c0fb735e713bc052ec0e4 (patch) | |
| tree | b8299e779e5afa33605984786dd3d02a0fa05a16 /llvm/lib/IR/Module.cpp | |
| parent | 248e88523518ae66a20d02bd3636cd0a15453958 (diff) | |
| download | llvm-afd42fb3038904e8c09c0fb735e713bc052ec0e4.zip llvm-afd42fb3038904e8c09c0fb735e713bc052ec0e4.tar.gz llvm-afd42fb3038904e8c09c0fb735e713bc052ec0e4.tar.bz2 | |
[AMDGPU][True16][CodeGen] Support AND/OR/XOR and LDEXP True16 format (#102620)
Support AND/OR/XOR true16 and LDEXP true/fake16 format.
These instructions are previously implemented with fake16 profile.
Fixing the implementation.
Added a RA hint so that when using 16bit register in a 32bit
instruction, try to use the register directly without an extra 16bit
move
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Co-authored-by: guochen2 <guochen2@amd.com>
Diffstat (limited to 'llvm/lib/IR/Module.cpp')
0 files changed, 0 insertions, 0 deletions