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| author | Jessica Paquette <jpaquette@apple.com> | 2021-06-10 14:40:18 -0700 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2021-06-10 15:29:51 -0700 |
| commit | 933df6ca796c0ace889bcc64706ec53462bd859a (patch) | |
| tree | 1bf8dbb9981391df085a8a7bc9567fec5bdf15e8 /llvm/lib/IR/Module.cpp | |
| parent | 4f6ec382c8b7204f3b1f48060025f970925f5804 (diff) | |
| download | llvm-933df6ca796c0ace889bcc64706ec53462bd859a.zip llvm-933df6ca796c0ace889bcc64706ec53462bd859a.tar.gz llvm-933df6ca796c0ace889bcc64706ec53462bd859a.tar.bz2 | |
[AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF
This adds legalization for scalar G_CTTZ and G_CTTZ_ZERO_UNDEF. Vector support
requires handling vector G_BITREVERSE, which I haven't gotten around to yet.
For G_CTTZ_ZERO_UNDEF, we just lower it to G_CTTZ.
For G_CTTZ, we match SelectionDAG's lowering to a G_BITREVERSE + G_CTLZ.
e.g. https://godbolt.org/z/nPEseYh1s
(With this patch, we have slightly worse codegen than SDAG for types smaller
than s32; it seems like we're missing a combine.)
Also, this adds in a function to build G_BITREVERSE to MachineIRBuilder.
Differential Revision: https://reviews.llvm.org/D104065
Diffstat (limited to 'llvm/lib/IR/Module.cpp')
0 files changed, 0 insertions, 0 deletions