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authorJay Foad <jay.foad@amd.com>2021-12-02 12:25:00 +0000
committerJay Foad <jay.foad@amd.com>2021-12-04 10:32:11 +0000
commitc8e84c7a5f38d46e97debba0eb1ae05f6a2fa39f (patch)
treef5857e14f4870e6a2eee8ab339cbff558b554be7 /llvm/lib/IR/Function.cpp
parentbc7dacf58946f62eaa533ee5d43365ec6bf10e12 (diff)
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[IR,TableGen] Add support for vec3 intrinsic arguments
Add generic support for vec3 types, and in particular define llvm_v3f32_ty which will be used by AMDGPU's llvm.amdgcn.image.bvh.intersect.ray intrinsic. Differential Revision: https://reviews.llvm.org/D114956
Diffstat (limited to 'llvm/lib/IR/Function.cpp')
-rw-r--r--llvm/lib/IR/Function.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp
index 82b20a8..63c8545 100644
--- a/llvm/lib/IR/Function.cpp
+++ b/llvm/lib/IR/Function.cpp
@@ -980,7 +980,8 @@ enum IIT_Info {
IIT_STRUCT9 = 49,
IIT_V256 = 50,
IIT_AMX = 51,
- IIT_PPCF128 = 52
+ IIT_PPCF128 = 52,
+ IIT_V3 = 53,
};
static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
@@ -1056,6 +1057,10 @@ static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
OutputTable.push_back(IITDescriptor::getVector(2, IsScalableVector));
DecodeIITType(NextElt, Infos, Info, OutputTable);
return;
+ case IIT_V3:
+ OutputTable.push_back(IITDescriptor::getVector(3, IsScalableVector));
+ DecodeIITType(NextElt, Infos, Info, OutputTable);
+ return;
case IIT_V4:
OutputTable.push_back(IITDescriptor::getVector(4, IsScalableVector));
DecodeIITType(NextElt, Infos, Info, OutputTable);