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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-06-29 12:18:27 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-06-29 12:19:05 +0100 |
| commit | 3521ecf1f8a3cf5e4811f93a9a809fc722462bbf (patch) | |
| tree | 78baacc782547a33fc710d8d8fd17b708725058a /llvm/lib/IR/DataLayout.cpp | |
| parent | 7f3d9cc1c059688b70cb35e673100c9eeadc4c46 (diff) | |
| download | llvm-3521ecf1f8a3cf5e4811f93a9a809fc722462bbf.zip llvm-3521ecf1f8a3cf5e4811f93a9a809fc722462bbf.tar.gz llvm-3521ecf1f8a3cf5e4811f93a9a809fc722462bbf.tar.bz2 | |
[X86] Add vector support to targetShrinkDemandedConstant for OR/XOR opcodes
If a constant is only allsignbits in the demanded/active bits, then sign extend it to an allsignbits bool pattern for OR/XOR ops.
This also requires SimplifyDemandedBits XOR handling to be modified to call ShrinkDemandedConstant on any (non-NOT) XOR pattern to account for non-splat cases.
Next step towards fixing PR45808 - with this patch we now get a <-1,-1,0,0> v4i64 constant instead of <1,1,0,0>.
Differential Revision: https://reviews.llvm.org/D82257
Diffstat (limited to 'llvm/lib/IR/DataLayout.cpp')
0 files changed, 0 insertions, 0 deletions