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authorDavid Green <david.green@arm.com>2023-01-09 11:52:37 +0000
committerDavid Green <david.green@arm.com>2023-01-09 11:52:37 +0000
commit07d6af6a71001c3d3a7aae21085646e642fbb56c (patch)
treedaf0325147e0fe0ef381d18a1d9f64d9214dc302 /llvm/lib/IR/Attributes.cpp
parent6d839621da8d0d85552c741c4c72369b4ada97c4 (diff)
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[AArch64] Fold And/Or into CSel if possible
If we have `and x, (csel 0, 1, cc)` and we know that x is 0/1, then we can emit a `csel ZR, x, cc`. Similarly for `or x, (csel 0, 1, cc)` we can emit `csinc x, ZR, cc`. This can help where we can not otherwise general ccmp instructions. Differential Revision: https://reviews.llvm.org/D141119
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