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| author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2021-08-26 09:42:06 -0400 |
|---|---|---|
| committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2021-08-31 22:29:11 -0400 |
| commit | 6a75041a1614af1ca787af5a18ea9ddbe4dd5c16 (patch) | |
| tree | ac16e7d87e5d2aa5242cb3ba095256b3068bae20 /llvm/lib/FileCheck/FileCheck.cpp | |
| parent | 89424a829f3c194177411c922c7050946891fff4 (diff) | |
| download | llvm-6a75041a1614af1ca787af5a18ea9ddbe4dd5c16.zip llvm-6a75041a1614af1ca787af5a18ea9ddbe4dd5c16.tar.gz llvm-6a75041a1614af1ca787af5a18ea9ddbe4dd5c16.tar.bz2 | |
[TableGen] Allow target specific flags for RegisterClass
Analogous to the TSFlags for machine instructions, this
patch introduces a bit vector for register classes to have
target specific flags that become a tablegened value in
TargetRegisterClass.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D108767
Diffstat (limited to 'llvm/lib/FileCheck/FileCheck.cpp')
0 files changed, 0 insertions, 0 deletions