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| author | Craig Topper <craig.topper@intel.com> | 2018-09-29 17:49:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-09-29 17:49:42 +0000 |
| commit | 716e8e6858222a1783bd62e10e7f26491cd2cd4f (patch) | |
| tree | 902e406e7bcee679dc124c340185d5fee23988b3 /llvm/lib/ExecutionEngine/Orc/ThreadSafeModule.cpp | |
| parent | a93407fadfe601f28e0a2df5e7946195f4f414c4 (diff) | |
| download | llvm-716e8e6858222a1783bd62e10e7f26491cd2cd4f.zip llvm-716e8e6858222a1783bd62e10e7f26491cd2cd4f.tar.gz llvm-716e8e6858222a1783bd62e10e7f26491cd2cd4f.tar.bz2 | |
[X86] Add more of the icc unaligned load/store to/from 128 bit vector intrinsics
Summary:
This patch adds
_mm_loadu_si32
_mm_loadu_si16
_mm_storeu_si64
_mm_storeu_si32
_mm_storeu_si16
We already had _mm_load_si64.
Reviewers: spatel, RKSimon
Reviewed By: RKSimon
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D52665
llvm-svn: 343388
Diffstat (limited to 'llvm/lib/ExecutionEngine/Orc/ThreadSafeModule.cpp')
0 files changed, 0 insertions, 0 deletions