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| author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2021-09-23 00:08:14 -0400 |
|---|---|---|
| committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2021-09-23 23:07:35 -0400 |
| commit | 40ddde5d1fa7e5eadb76f6c3cc37dae2f80a8ca2 (patch) | |
| tree | 4ca296ad68ba2406a86c1da9f4fbdd5aa0bdaea3 /llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp | |
| parent | 58d9ed2c935d6665da388cd72273360349792281 (diff) | |
| download | llvm-40ddde5d1fa7e5eadb76f6c3cc37dae2f80a8ca2.zip llvm-40ddde5d1fa7e5eadb76f6c3cc37dae2f80a8ca2.tar.gz llvm-40ddde5d1fa7e5eadb76f6c3cc37dae2f80a8ca2.tar.bz2 | |
[TableGen] Allow targets to entirely ignore Psets for registers
Tablegen currently expects targets to have at least one
pressure set for every broader register category. AMDGPU's
VGPR or AGPR, for instance, seemed to work correctly without
any pset, though we have forced one for each type to avoid
the assertion in computeRegUnitSets. However, psets can not
be entirely empty. At least one set is mandatory for every
target. This patch bypasses the assertion for the classes
when GeneratePressureSet is zero while ensuring the
RegUnitSets are not empty.
Reviewed By: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D110305
Diffstat (limited to 'llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp')
0 files changed, 0 insertions, 0 deletions