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| author | Carl Ritson <carl.ritson@amd.com> | 2021-06-08 11:10:53 +0900 |
|---|---|---|
| committer | Carl Ritson <carl.ritson@amd.com> | 2021-06-08 11:11:40 +0900 |
| commit | f8816c7400250961af4810956248c3636a5fcb04 (patch) | |
| tree | 9a84150a83f8607e2641803a0c52f047bd882e3b /llvm/lib/Demangle/RustDemangle.cpp | |
| parent | e6629be31e67190f0a524f009752d73410894560 (diff) | |
| download | llvm-f8816c7400250961af4810956248c3636a5fcb04.zip llvm-f8816c7400250961af4810956248c3636a5fcb04.tar.gz llvm-f8816c7400250961af4810956248c3636a5fcb04.tar.bz2 | |
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
Avoid having to round up to v8f32/VReg_256 when only 5 VGPRs are
required for a MIMG address operand.
Maintain _V8 instruction variants of pseudo instructions allowing
assembly prior to GFX10 to work as-is. Currently the validator
can tell for GFX10 what the correct size is, so will disallow
oversize address registers.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D103672
Diffstat (limited to 'llvm/lib/Demangle/RustDemangle.cpp')
0 files changed, 0 insertions, 0 deletions