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| author | Craig Topper <craig.topper@intel.com> | 2018-03-19 19:00:32 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-19 19:00:32 +0000 |
| commit | b4c7873f8cb8131fdef833e6abfaac4261930f54 (patch) | |
| tree | 5b155947df93827ef25fcc78fd620c65b045a273 /llvm/lib/DebugInfo/CodeView/DebugCrossImpSubsection.cpp | |
| parent | afabf36505542776a2a2b4e70c91687b163b45aa (diff) | |
| download | llvm-b4c7873f8cb8131fdef833e6abfaac4261930f54.zip llvm-b4c7873f8cb8131fdef833e6abfaac4261930f54.tar.gz llvm-b4c7873f8cb8131fdef833e6abfaac4261930f54.tar.bz2 | |
[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models.
JRCXZ was already present, but not the others.
We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output.
llvm-svn: 327881
Diffstat (limited to 'llvm/lib/DebugInfo/CodeView/DebugCrossImpSubsection.cpp')
0 files changed, 0 insertions, 0 deletions