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| author | Artem Belevich <tra@google.com> | 2018-03-20 17:18:59 +0000 |
|---|---|---|
| committer | Artem Belevich <tra@google.com> | 2018-03-20 17:18:59 +0000 |
| commit | 914d4babec358a845a31f30a50ee729393593f3d (patch) | |
| tree | aed987b58941c857aa3f68e4d5c81965ee8e99f6 /llvm/lib/DebugInfo/CodeView/DebugCrossImpSubsection.cpp | |
| parent | 3a9989361898266e5279d1d91055ff63b00d041d (diff) | |
| download | llvm-914d4babec358a845a31f30a50ee729393593f3d.zip llvm-914d4babec358a845a31f30a50ee729393593f3d.tar.gz llvm-914d4babec358a845a31f30a50ee729393593f3d.tar.bz2 | |
[NVPTX] Make tensor load/store intrinsics overloaded.
This way we can support address-space specific variants without explicitly
encoding the space in the name of the intrinsic. Less intrinsics to deal with ->
less boilerplate.
Added a bit of tablegen magic to match/replace an intrinsics with a pointer
argument in particular address space with the space-specific instruction
variant.
Updated tests to use non-default address spaces.
Differential Revision: https://reviews.llvm.org/D43268
llvm-svn: 328006
Diffstat (limited to 'llvm/lib/DebugInfo/CodeView/DebugCrossImpSubsection.cpp')
0 files changed, 0 insertions, 0 deletions