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authorSimon Pilgrim <llvm-dev@redking.me.uk>2025-08-06 14:55:46 +0100
committerGitHub <noreply@github.com>2025-08-06 14:55:46 +0100
commitc4f6d346749cd368ab60fa06d925b15934d0e38a (patch)
tree660c6eb731c5c7dd287dc0e27ba40eae16a4f3e3 /llvm/lib/CodeGen
parentded1f3ec96bc3de2951094dff5a8d2e12f7402c8 (diff)
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[DAG] getNode - fold (sext (trunc x)) -> x iff the upper bits are already signbits (#151945)
Similar to what we already do for ZERO_EXTEND/ANY_EXTEND patterns.
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp14
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 71a175d..649a310 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6422,6 +6422,20 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
if (N1.isUndef())
// sext(undef) = 0, because the top bits will all be the same.
return getConstant(0, DL, VT);
+
+ // Skip unnecessary sext_inreg pattern:
+ // (sext (trunc x)) -> x iff the upper bits are all signbits.
+ if (OpOpcode == ISD::TRUNCATE) {
+ SDValue OpOp = N1.getOperand(0);
+ if (OpOp.getValueType() == VT) {
+ unsigned NumSignExtBits =
+ VT.getScalarSizeInBits() - N1.getScalarValueSizeInBits();
+ if (ComputeNumSignBits(OpOp) > NumSignExtBits) {
+ transferDbgValues(N1, OpOp);
+ return OpOp;
+ }
+ }
+ }
break;
case ISD::ZERO_EXTEND:
assert(VT.isInteger() && N1.getValueType().isInteger() &&