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| author | Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> | 2024-04-29 11:11:59 +0200 |
|---|---|---|
| committer | Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> | 2024-04-29 13:08:52 +0200 |
| commit | 55c6bda01ef5a166a69b43956775272d9d67bda5 (patch) | |
| tree | 16786fd8285a4687d662e6e28401cbce3a434d5c /llvm/lib/CodeGen | |
| parent | 95395ee51124792302390305b02cbeace5f07611 (diff) | |
| download | llvm-55c6bda01ef5a166a69b43956775272d9d67bda5.tar.gz llvm-55c6bda01ef5a166a69b43956775272d9d67bda5.tar.bz2 llvm-55c6bda01ef5a166a69b43956775272d9d67bda5.zip | |
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
This reverts commit 16bd10a38730fed27a3bf111076b8ef7a7e7b3ee.
Re-applies:
b3c55b707110084a9f50a16aade34c3be6fa18da - "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)"
8e2f6495c0bac1dd6ee32b6a0d24152c9c343624 - "[DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)"
73472c5996716cda0dbb3ddb788304e0e7e6a323 - "[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)"
with a fix in DAGCombiner::visitFREEZE.
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 26 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 17 |
2 files changed, 42 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f8949b926922..4b81185c6e31 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -15459,6 +15459,12 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false)) return N0; + // We currently avoid folding freeze over SRA/SRL, due to the problems seen + // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for + // example https://reviews.llvm.org/D136529#4120959. + if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) + return SDValue(); + // Fold freeze(op(x, ...)) -> op(freeze(x), ...). // Try to push freeze through instructions that propagate but don't produce // poison as far as possible. If an operand of freeze follows three @@ -15475,6 +15481,26 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { N0.getOpcode() == ISD::BUILD_PAIR || N0.getOpcode() == ISD::CONCAT_VECTORS; + // Avoid turning a BUILD_VECTOR that can be recognized as "all zeros", "all + // ones" or "constant" into something that depends on FrozenUndef. We can + // instead pick undef values to keep those properties, while at the same time + // folding away the freeze. + // If we implement a more general solution for folding away freeze(undef) in + // the future, then this special handling can be removed. + if (N0.getOpcode() == ISD::BUILD_VECTOR) { + SDLoc DL(N0); + EVT VT = N0.getValueType(); + if (llvm::ISD::isBuildVectorAllOnes(N0.getNode())) + return DAG.getAllOnesConstant(DL, VT); + if (llvm::ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) { + SmallVector<SDValue, 8> NewVecC; + for (const SDValue &Op : N0->op_values()) + NewVecC.push_back( + Op.isUndef() ? DAG.getConstant(0, DL, Op.getValueType()) : Op); + return DAG.getBuildVector(VT, DL, NewVecC); + } + } + SmallSetVector<SDValue, 8> MaybePoisonOperands; for (SDValue Op : N0->ops()) { if (DAG.isGuaranteedNotToBeUndefOrPoison(Op, /*PoisonOnly*/ false, diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 224c0c5ee970..dfbfaa8c894f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5063,6 +5063,7 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, case ISD::VALUETYPE: case ISD::FrameIndex: case ISD::TargetFrameIndex: + case ISD::CopyFromReg: return true; case ISD::UNDEF: @@ -5136,6 +5137,16 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, case ISD::FREEZE: case ISD::CONCAT_VECTORS: case ISD::INSERT_SUBVECTOR: + case ISD::SADDSAT: + case ISD::UADDSAT: + case ISD::SSUBSAT: + case ISD::USUBSAT: + case ISD::MULHU: + case ISD::MULHS: + case ISD::SMIN: + case ISD::SMAX: + case ISD::UMIN: + case ISD::UMAX: case ISD::AND: case ISD::XOR: case ISD::ROTL: @@ -5156,6 +5167,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, case ISD::BUILD_PAIR: return false; + case ISD::SELECT_CC: case ISD::SETCC: { // Integer setcc cannot create undef or poison. if (Op.getOperand(0).getValueType().isInteger()) @@ -5165,7 +5177,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, // based on options and flags. The options and flags also cause special // nonan condition codes to be used. Those condition codes may be preserved // even if the nonan flag is dropped somewhere. - ISD::CondCode CCCode = cast<CondCodeSDNode>(Op.getOperand(2))->get(); + unsigned CCOp = Opcode == ISD::SETCC ? 2 : 4; + ISD::CondCode CCCode = cast<CondCodeSDNode>(Op.getOperand(CCOp))->get(); if (((unsigned)CCCode & 0x10U)) return true; @@ -5182,6 +5195,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, return false; case ISD::SHL: + case ISD::SRL: + case ISD::SRA: // If the max shift amount isn't in range, then the shift can create poison. return !getValidMaximumShiftAmountConstant(Op, DemandedElts); |
